1. Field of the Invention
The present invention relates to a liquid crystal display device used for the display device of a computer and so forth, and more particularly, to a drive circuit of a liquid crystal display device suitably used for the drive circuit of a liquid crystal panel.
2. Prior Art
In recent years, liquid crystal display devices using liquid crystal panels which are able to comparatively effectively realize brightness and high resolution more than cathode ray tubes (CRTs), have come to be used as display devices of computers, portable terminals and so forth.
FIG. 10 is a block diagram showing the configuration of a drive circuit of the prior art that drives a liquid crystal panel of a liquid crystal display device. In this drawing, 1 is a liquid crystal panel that displays images, 101 is a controller that outputs image data displayed by liquid crystal panel 1 from one port in the form of 48-bit data BUS1 to 48 via a 48-bit bus line, and 102-m (m is an integer of 1 or more) is a source driver (abbreviated as SD) that drives liquid crystal panel 1 by generating drive signals for displaying images from data BUS1 to 48 output by this controller 101.
Furthermore, the following explanation is given for the case of m, which indicates the number of this SD, being 10. In addition, SD102-5 through SD102-10 are not shown in FIG. 10.
Data BUS1 to 24 output by controller 101 shown in FIG. 10 are connected to each odd-numbered SD102-1, 3, 5, 7 and 9 among SD102-1 through SD102-10. Similarly, clock CLK3 and control signal SP3 output by controller 101 are also connected to each odd-numbered SD102-1, 3, 5, 7 and 9.
On the other hand, data BUS25 to 48 output by controller 101 are connected to each even-numbered SD102-2, 4, 6, 8 and 10 of SD102-1 through SD102-10, and similarly, clock CLK4 and control signal SP4 output by controller 101 are also connected to each even-numbered SD102-2, 4, 6, 8 and 10.
Furthermore, a breakdown of the respective 24-bit signals of the above data BUS1 to 24 and data BUS25 to 48 consists of red (R), green (G) and blue (B) signals of 8 bits each, and a color display of 256 gradations is realized by these R, G and B signals.
In this drive circuit of a liquid crystal display device of the prior art composed in this manner, each odd-numbered SD102-1, 3, 5, 7 and 9 respectively latches data BUS1 to 24 output from controller 101 in synchronization with clock CLK3 at the time of control signal SP3. On the other hand, each even-numbered SD102-2, 4, 6, 8 and 10 respectively latches data BUS25 to 48 output from controller 101 in synchronization with clock CLK4 at the time of control signal SP4.
Next, each SD102-1 through SD102-10 generates a drive signal based on latched data BUS1 to 24 or BUS25 to 48, respectively, when each drive starting signal (not shown), which designates the start of driving to liquid crystal panel 1, is input. When a drive signal generated by each of these SD102-1 through SD102-10 is input to liquid crystal panel 1, an image is displayed on that liquid crystal panel 1.
Furthermore, there are fixed limitations on the frequencies of input clocks CLK3 and 4, which are the transfer frequencies of image data, for SD102-1 through SD102-10 that drive liquid crystal panel 1. In order to lower the transfer frequency of image data to equal to or less than that limiting frequency, the bus line that transfers image data from controller 101 to each SD102-1 through SD102-10 is divided into 24 bits each, and transfers image data to each odd-numbered SD102-1, 3, 5, 7 and 9, and each even-numbered SD102-2, 4, 6, 8 and 10, respectively.
However, in the drive circuit of a liquid crystal display device of the prior art described above, if the amount of change in the value of each bit of data BUS1 to 48 transferred on the bus lines is excessively large, the problem results in which the power consumption of the drive circuit of the liquid crystal display device becomes large.
In addition, the bus lines that transfer data BUS1-48 becomes long since they run in the horizontal direction around liquid crystal panel 1. In addition, since the number of bus lines is also large, there are cases in which antenna effects result. Consequently, if the amount of change in the value of each bit of data BUS1 to 48 transferred on that bus line is excessively large, electromagnetic interference noise that is radiated due to the changes in the value of each bit also becomes large resulting in poor electromagnetic interference (EMI) characteristics. Since this radiated electromagnetic interference can cause erroneous operation and have other detrimental effects on surrounding electronic equipment, poor EMI characteristics of liquid crystal display devices used in the vicinity of precision electronic equipment or in computer rooms and so forth can present an extremely serious problem.
Moreover, it is necessary to use expensive anti-EMI components to reduce radiation of this electromagnetic interference, which in turn increases the cost of liquid crystal display devices.
Moreover, it is difficult to determine whether or not this radiated electromagnetic interference is noise that originates in the bus line, and being unable to identify the cause of its radiation is also a problem.
In addition, in the case of a large amount of change in the values of each bit of data BUS1-48, cross-talk noise occurs between bus lines resulting in the problem of causing data errors.
The present invention takes into consideration these circumstances, and its object is to provide a drive circuit of a liquid crystal display device that transfers image data to a liquid crystal panel which is able to reduce the amount of change in the values of each bit of data transferred over bus lines.
In order to solve the above problems, a first exemplary embodiment of the invention is a drive circuit of a liquid crystal display device having a bus line of a width equal to the number of transfer data signals and to which is output a plurality of transfer data signals; equipped with: a data polarity inversion judgment device, which outputs a polarity inversion signal indicating that the plurality of data signals are output to the bus line after inverting the polarity of all the signals in the case the majority or more of a plurality of data signals output to the bus line as the plurality of transfer data signals cause a polarity change in the output to the bus line; and, a polarity inversion device that inverts the polarity of all of the plurality of data signals that are input and outputs the signals as the plurality of transfer data signals corresponding to the polarity inversion signal output from the data polarity inversion judgment device.
In a second exemplary embodiment, the above data polarity inversion judgment device and the above polarity inversion device are respectively equipped for a plurality of bus lines.
In a third exemplary embodiment, a drive circuit of a liquid crystal display device having a bus line of a width equal to the number of transfer data signals and to which is output a plurality of transfer data signals; equipped with: a first latching circuit that latches a plurality of input data signals in synchronization with an input clock and outputs signals in the form of a plurality of first data signals; a polarity inversion circuit that inverts the polarity of all of the plurality of first data signals and outputs the signals in the form of a plurality of second data signals in the case an input first polarity inversion signal is at a predetermined inversion designation level; a data polarity inversion judgment circuit that outputs a second polarity inversion signal in the form of the inversion designation level in the case the number of corresponding plurality of input data signals and plurality of second data signals having different polarity is greater than or equal to the majority of the signals; and, a second latching circuit that latches the second polarity inversion signal in synchronization with the input clock, and outputs the signal in the form of the first polarity inversion signal.
A fourth exemplary embodiment is equipped with: a third latching circuit that latches that plurality of second data signals in synchronization with the input clock and outputs the signals in the form of the plurality of transfer data signals; and, a fourth latching circuit that latches the first polarity inversion signal in synchronization with the input clock and outputs the signal in the form of a third polarity inversion signal.
In a fifth exemplary embodiment the above first to fourth latching circuits, the above polarity inversion circuit and the above data polarity inversion judgment circuit are respectively equipped for a plurality of bus lines.
In a sixth exemplary embodiment the phase of the above input clock corresponding to half the number of the plurality of bus lines, and the phase of the above input clock corresponding to the other half of the number of the plurality of bus lines are out of phase by one half cycle.